Yield, power and performance optimization for low power clock network under parametric variations in nanometer scale design

被引：0

作者：

Chawla, Tarun ^{[1
]}

Amara, Amara ^{[1
]}

Vladimirescu, Andrei ^{[1
]}

机构：

[1] Inst Super Elect Paris, Dept Elect, 21 Rue Assas, F-75006 Paris, France

来源：

IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II | 2006年

关键词：

D O I：

10.1109/MWSCAS.2006.382252

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Advancing in the nanometer regime, parametric variations has made yield a critical parameter to be included right in the beginning of the design process. Low power circuits have to be designed keeping in mind power consumption, minimum performance levels and yield and find the best compromise between all three. Statistical techniques, Monte Carlo Analysis, using log-normal model has been used to study the effect of parametric variations in leakage dominant 65 nm clock network design. Power supply (Vdd) and threshold voltage (Vth) scaling along with length and device sizing optimization is used to achieve best compromise among power consumption, delay and yield depending on the target application. General guidelines based on final application are given.

引用

页码：231 / +

页数：2

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