Topology adaptive network-on-chip design and implementation

被引:29
|
作者
Bartic, TA
Mignolet, JY
Nollet, V
Marescaux, T
Verkest, D
Vernalde, S
Lauwereins, R
机构
[1] IMEC, B-3001 Louvain, Belgium
[2] Katholieke Univ Leuven, Louvain, Belgium
[3] Vrije Univ Brussels, Brussels, Belgium
来源
关键词
D O I
10.1049/ip-cdt:20045016
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs in solving the numerous technological, economic and productivity problems associated with billion-transistor system-on-chip development. The authors believe that different types of networks will be required, depending on the application domain. Therefore, a very flexible network design is proposed that is highly scalable, and can be easily changed to accomodate various needs. A network-on-chip design, realised as part of the platform that the authors are developing for reconfigurable systems, is presented. This design is suitable for building networks with irregular topologies, and with low latency and high throughput.
引用
收藏
页码:467 / 472
页数:6
相关论文
共 50 条
  • [31] Network-on-chip architectures and design methods
    Benini, L
    Bertozzi, D
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2005, 152 (02): : 261 - 272
  • [32] Hierarchical network-on-chip design method
    Microprocessor Research and Development Center, Peking University, Beijing 100871, China
    Beijing Daxue Xuebao Ziran Kexue Ban, 2007, 5 (669-676):
  • [33] Design and Evaluation of Efficient Router Architecture for Triplet-Based Network-on-Chip Topology
    Zhang, Yang
    JOURNAL OF TESTING AND EVALUATION, 2014, 42 (06) : 1323 - 1334
  • [34] AdNoC: Runtime Adaptive Network-on-Chip Architecture
    Al Faruque, Mohammad Abdullah
    Ebi, Thomas
    Henkel, Joerg
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (02) : 257 - 269
  • [35] Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
    Kundu, Santanu
    Chattopadhyay, Santanu
    International Journal of High Performance Systems Architecture, 2008, 1 (03) : 163 - 182
  • [36] Communication analysis for network-on-chip design
    Siebenborn, A
    Bringmann, O
    Rosenstiel, W
    INTERNATIONAL CONFERENCE ON PARALLEL COMPUTING IN ELECTRICAL ENGINEERING, 2004, : 315 - 320
  • [37] Heterogeneous design methodology with configurable regular topology set for scalable Network-on-Chip designs
    Chen, Wentao
    Jin, Depeng
    Zeng, Lieguang
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1293 - 1296
  • [38] Network-on-chip architectures and design methodologies
    Palesi, Maurizio
    Kumar, Shashi
    Marculescu, Radu
    MICROPROCESSORS AND MICROSYSTEMS, 2011, 35 (02) : 83 - 84
  • [39] Fault-Tolerant Application Mapping on to ZMesh topology based Network-on-Chip Design
    Bhanu, P. Veda
    Mandapati, Nikita
    Soumya, J.
    Cenkeramaddi, Linga Reddy
    PROCEEDINGS OF THE 15TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS (ICIEA 2020), 2020, : 142 - 147
  • [40] A Novel Adaptive Routing Algorithm for Network-on-Chip
    Jia, Jia
    Zhou, Duan
    Zhang, Jianxian
    ADVANCED MATERIALS AND COMPUTER SCIENCE, PTS 1-3, 2011, 474-476 : 413 - +