A fast-locked all-digital delay-locked loop with non-50% input duty cycle

被引：0
|
作者：
Kao, Shao-Ku [1 ]
Chen, Bo-Jiun [1 ]
Liu, Shen-Luan [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
来源：
EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS | 2007年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A fast-locked all-digital delay-locked loop (DLL) with 50% output duty cycle is presented. A delay line using TSPC DFFs is re-used for the DLL and a time-to-digital converter. It results in a small-area and fast-locked DLL. The proposed DLL generates the output clock with 50% duty cycle in 4 cycles This DLL has been fabricated in a 0.18um process. The core area is 350umx105um. The measured input frequency range is from 300MHz to 500MHz with input duty cycle of 40%similar to 60%.
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收藏
页码：1125 / 1128
页数：4
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