Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

被引:21
|
作者
Kundu, Atanu [1 ]
Koley, Kalyan [2 ]
Dutta, Arka [2 ]
Sarkar, Chandan K. [2 ]
机构
[1] Heritage Inst Technol, Elect & Commun Engn Dept, Kolkata 700107, India
[2] Jadavpur Univ, Elect & Telecommun Engn Dept, Nano Device Simulat Lab, Kolkata 700032, India
关键词
Subthreshold analog; Symmetric underlap DG FET; Dual metal gate double gate (DMG-DG); Carrier transport efficiency; Work-function; FRINGE CAPACITANCE; FREQUENCY NOISE; SILICON; MOSFET; DGMOS;
D O I
10.1016/j.microrel.2014.08.009
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g(m)), the gain per unit current (g(m)/I-ds), the intrinsic gain (g(m)R(o)), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RE performance analysis. Analysis suggested that the average intrinsic gain, g(m)/I-d and g(m) are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:2717 / 2722
页数:6
相关论文
共 50 条
  • [21] Impact of Drain Underlap and High Bandgap Strip on Cylindrical Gate All Around Tunnel FET and its Influence on Analog/RF Performance
    Dutt, Arya
    Tiwari, Sanjana
    Upadhyay, Abhishek Kumar
    Mathew, Ribu
    Beohar, Ankur
    SILICON, 2022, 14 (15) : 9789 - 9796
  • [22] Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High-k Spacer for Low Power Applications
    Koley, Kalyan
    Dutta, Arka
    Syamal, Binit
    Saha, Samar K.
    Sarkar, Chandan Kumar
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (01) : 63 - 69
  • [23] Study the impact of graphene channel over conventional silicon on DC/analog and RF performance of DG dual-material-gate VTFET
    Zohmingliana
    Choudhuri, Bijit
    Bhowmick, Brinda
    MICROELECTRONICS JOURNAL, 2022, 128
  • [24] Electrostatic performance improvement of dual material cylindrical gate MOSFET using work-function modulation technique
    Jena, Biswajit
    Dash, Sidhartha
    Mishra, Guru Prasad
    SUPERLATTICES AND MICROSTRUCTURES, 2016, 97 : 212 - 220
  • [25] Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes
    Satish K. Das
    Umakanta Nanda
    Sudhansu M. Biswal
    Chandan Kumar Pandey
    Lalat Indu Giri
    Silicon, 2022, 14 : 2965 - 2973
  • [26] Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes
    Das, Satish K.
    Nanda, Umakanta
    Biswal, Sudhansu M.
    Pandey, Chandan Kumar
    Giri, Lalat Indu
    SILICON, 2022, 14 (06) : 2965 - 2973
  • [27] Impact of the Metal-Gate Material Properties in FinFET (Versus FD-SOI MOSFET) on High-κ/Metal Gate Work-Function Variation
    Nam, Hyohyun
    Shin, Changhwan
    Park, Jung-Dong
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (11) : 4780 - 4785
  • [28] On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI
    Franco, J.
    Wu, Z.
    Rzepa, G.
    Ragnarsson, L. -A.
    Dekkers, H.
    Vandooren, A.
    Groeseneken, G.
    Horiguchi, N.
    Collaert, N.
    Linten, D.
    Grasser, T.
    Kaczer, B.
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2019, 19 (02) : 268 - 274
  • [29] The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor
    S.Intekhab Amin
    R.K.Sarin
    Journal of Semiconductors, 2015, 36 (09) : 51 - 57
  • [30] The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor
    Amin, S. Intekhab
    Sarin, R. K.
    JOURNAL OF SEMICONDUCTORS, 2015, 36 (09)