Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

被引:21
|
作者
Kundu, Atanu [1 ]
Koley, Kalyan [2 ]
Dutta, Arka [2 ]
Sarkar, Chandan K. [2 ]
机构
[1] Heritage Inst Technol, Elect & Commun Engn Dept, Kolkata 700107, India
[2] Jadavpur Univ, Elect & Telecommun Engn Dept, Nano Device Simulat Lab, Kolkata 700032, India
关键词
Subthreshold analog; Symmetric underlap DG FET; Dual metal gate double gate (DMG-DG); Carrier transport efficiency; Work-function; FRINGE CAPACITANCE; FREQUENCY NOISE; SILICON; MOSFET; DGMOS;
D O I
10.1016/j.microrel.2014.08.009
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g(m)), the gain per unit current (g(m)/I-ds), the intrinsic gain (g(m)R(o)), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RE performance analysis. Analysis suggested that the average intrinsic gain, g(m)/I-d and g(m) are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:2717 / 2722
页数:6
相关论文
共 50 条
  • [31] Influence of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET for Improved Analog/RF Performance
    Venkatesh, M.
    Suguna, M.
    Balamurugan, N. B.
    SILICON, 2020, 12 (12) : 2869 - 2877
  • [32] Influence of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET for Improved Analog/RF Performance
    M. Venkatesh
    M. Suguna
    N. B. Balamurugan
    Silicon, 2020, 12 : 2869 - 2877
  • [33] Analysis of Metal gate Work-Function Variation for Vertical Nanoplate FET in 6-T SRAMs
    Ko, Kyul
    Son, Dokyun
    Kang, Myounggon
    Shin, Hyungcheol
    2017 SILICON NANOELECTRONICS WORKSHOP (SNW), 2017, : 61 - 62
  • [34] Impact of Interface Charges on the Performance of Dual Material Double Gate Tunnel FET
    Noor, Samantha Lubaba
    Safa, Samia
    Khan, Md. Ziaur Rahman
    2016 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2016, : 170 - 173
  • [35] Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET
    Malihe Zare
    Fateme Peyravi
    Seyed Ebrahim Hosseini
    Journal of Electronic Materials, 2020, 49 : 5638 - 5646
  • [36] Comparative Study of Variations in Gate Oxide Material of a Novel Underlap DG MOS-HEMT for Analog/RF and High Power Applications
    Mondal, Arnab
    Roy, Akash
    Mitra, Rajrup
    Kundu, Atanu
    SILICON, 2020, 12 (09) : 2251 - 2257
  • [37] Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET
    Zare, Malihe
    Peyravi, Fateme
    Hosseini, Seyed Ebrahim
    JOURNAL OF ELECTRONIC MATERIALS, 2020, 49 (09) : 5638 - 5646
  • [38] Comparative Study of Variations in Gate Oxide Material of a Novel Underlap DG MOS-HEMT for Analog/RF and High Power Applications
    Arnab Mondal
    Akash Roy
    Rajrup Mitra
    Atanu Kundu
    Silicon, 2020, 12 : 2251 - 2257
  • [39] Work-function Engineering in Gate First Technology for Multi-V T Dual-Gate FDSOI CMOS on UTBOX
    Weber, O.
    Andrieu, F.
    Mazurier, J.
    Casse, M.
    Garros, X.
    Leroux, C.
    Martin, F.
    Perreau, P.
    Fenouillet-Beranger, C.
    Barnola, S.
    Gassilloud, R.
    Arvet, C.
    Thomas, O.
    Noel, J-P.
    Rozeau, O.
    Jaud, M-A.
    Poiroux, T.
    Lafond, D.
    Toffoli, A.
    Allain, F.
    Tabone, C.
    Tosti, L.
    Brevard, L.
    Lehnen, P.
    Weber, U.
    Baumann, P. K.
    Boissiere, O.
    Schwarzenbach, W.
    Bourdelle, K.
    Nguyen, B-Y
    Boeuf, F.
    Skotnicki, T.
    Faynot, O.
    2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST, 2010,
  • [40] Enhancement in performance of poly-crystalline thin film transistors with gate dielectric and work-function
    Sehgal, A
    Mangla, T
    Chopra, S
    Gupta, M
    Gupta, RS
    THIN SOLID FILMS, 2006, 504 (1-2) : 55 - 58