Testing carry logic modules of SRAM-based FPGAs

被引：3

作者：

Sun, XL ^{[1
]}

Xu, J ^{[1
]}

Trouborst, P ^{[1
]}

机构：

[1] Univ Alberta, Dept Elect & Comp Engn, Edmonton, AB T6G 2G7, Canada

来源：

2001 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/MTDT.2001.945235

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The carry logic module (CLM) is an integral part of a configurable logic block (CLB) in a Xilinx XC4000 field programmable gate array (FPGA). This paper addresses the testing issues of a CLM for the first time. The integrity of a CLM is validated by, the integrity of fill its components. It has been found that the minimum numbers of CLM test configurations (TCs) under single stuck-at, multiple stuck-at, and universal fault models are six, seven and eight respectively. A set of selection criteria was proposed to obtain the "best" of eight TCs, each contains a subset of six and seven TCs for the two stuck-at fault models. These CLM TCs can be extended to include the test of the whole CLB.

引用

页码：91 / 98

页数：8

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