A 2 x 20-Gb/s, 1.2-pJ/bit, Time-Interleaved Optical Receiver in 40-nm CMOS

被引：0

作者：

Huang, Shih-Hao ^{[1
]}

Hung, Zheng-Hao ^{[1
]}

Chen, Wei-Zen ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu 30010, Taiwan

来源：

2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC) | 2014年

关键词：

Monolithic optical receiver; high-density optical interconnect; photodetector (PD); comparator;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a single-chip, 2 x 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1: 4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 mu A(pp) at bit-error-rate of less than 10(-12). Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 mm(2).

引用

页码：97 / 100

页数：4

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