On the fault testing for reversible circuits

被引：0
|
作者：
Tayu, Satoshi [1 ]
Ito, Shigeru [1 ]
Ueno, Shuichi [1 ]
机构：
[1] Tokyo Inst Technol, Dept Commun & Integrated Syst, Tokyo 1528550, Japan
来源：
ALGORITHMS AND COMPUTATION | 2007年 / 4835卷
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
This paper shows that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit. We also show non-trivial lower bounds for the size of a minimum complete test set.
引用
收藏
页码：812 / 821
页数：10
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