RAPANUI:: A case study in rapid prototyping for multiprocessor system-on-chip

被引：0

作者：

Paya-Vaya, Guillermo ^{[1
]}

Martin-Langerwerf, Javier ^{[1
]}

Pirsch, Peter ^{[1
]}

机构：

[1] Leibniz Univ Hannover, Inst Microelect Syst, Hannover, Germany

来源：

DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS | 2007年

关键词：

design verification and modeling; emulation; prototyping; case study;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes a case study in a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The goal of the presented methodology is to speed up and improve the verification flow of a multiprocessor system that will finally be implemented as an ASIC. The case study consists of a 64-bit compatible AMBA AHB system bus which connects up to 14.32-Bit RISC processors to a host interface. A typical parallel computing application has been implemented for the parameterized multiprocessor system. The employed FPGA emulation environment increases by up to 200 the simulation frequency of the global system on a workstation (2.2 GHz AMD Dual Opteron with 8 GB RAM). Moreover a stand-alone emulation can be performed at the maximum achievable frequency (65 MHz).

引用

页码：215 / 221

页数：7

共 50 条

[21] Broker Fault Recovery for a Multiprocessor System-on-Chip Middleware
Domingues, Anderson R. P.
Hamerski, Jean Carlo
Amory, Alexandre
2018 31ST SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI), 2018,
[22] Multiprocessor System-on-Chip Design for Industrial Wireless Application
Surantha, Nico
Maria, Astri
Nagao, Yuhei
Ochi, Hiroshi
2016 INTERNATIONAL SYMPOSIUM ON ELECTRONICS AND SMART DEVICES (ISESD), 2016, : 57 - 62
[23] Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
Phi-Hung Pham
Song, Junyoung
Park, Jongsun
Kim, Chulwoo
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (01) : 173 - 177
[24] A Case Study on Logic Diagnosis for System-on-Chip
Benabboud, Y.
Bosio, A.
Girard, P.
Pravossoudovitch, S.
Virazel, A.
Bouzaida, L.
Izaute, I.
ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2, 2009, : 253 - +
[25] Prototyping of a 5 GHz WLAN reconfigurable System-on-Chip
Blionas, S
Masselos, K
Dre, C
Drosos, C
Ieromnimon, F
Metafas, D
Pagonis, T
Pnevmatikakis, A
Tatsaki, A
Trimis, T
Vontzalidis, A
Vontzalidist, A
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2003, E86D (05) : 891 - 900
[26] PrSoC: Programmable System-on-chip (SoC) for silicon prototyping
Huang, Chun-Ming
Wu, Chien-Ming
Yang, Chih-Chyau
Wey, Chin-Long
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 3382 - 3385
[27] Architecture, On-Chip Network and Programming Interface Concept for Multiprocessor System-on-Chip
Samman, Faisal Arya
Dollak, Bjoern
Antoni, Jonatan
Hollstein, Thomas
2016 INTERNATIONAL CONFERENCE ON SMART GREEN TECHNOLOGY IN ELECTRICAL AND INFORMATION SYSTEMS (ICSGTEIS), 2016, : 155 - 160
[28] A rapid prototyping method for top-down design of system-on-chip devices using LPGAs
Suzuki, F
Koizumi, H
Seo, K
Yasuura, H
Hiramine, M
Okino, K
OrBach, Z
PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997, 1996, : 9 - 18
[29] RAPANUI:: Rapid prototyping for media processor architecture exploration
Váyá, GP
Langerwerf, JM
Pirsch, P
EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, 2005, 3553 : 32 - 40
[30] Interfacing UML 2.0 for multiprocessor System-on-Chip design flow
Riihimaki, Jouni
Kukkala, Petri
Kangas, Tero
Hannikainen, Marko
Hamalainen, Timo D.
2005 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2005, : 108 - 111

← 1 2 3 4 5 →