Dual-Channel Technology with Cap-free Single Metal Gate for High Performance CMOS in Gate-First and Gate-Last Integration

被引：0

作者：

Witters, L. ^{[1
]}

Mitard, J. ^{[1
]}

Veloso, A. ^{[1
]}

Hikavyy, A. ^{[1
]}

Franco, J. ^{[4
]}

Kauerauf, T. ^{[1
]}

Cho, M. ^{[1
]}

Schram, T. ^{[1
]}

Sebai, F. ^{[1
]}

Yamaguchi, S. ^{[5
]}

Takeoka, S. ^{[6
]}

Fukuda, M. ^{[7
]}

Wang, W. -E. ^{[1
]}

Duriez, B. ^{[1
]}

Eneman, G. ^{[3
,4
]}

Loo, R. ^{[1
]}

Kellens, K. ^{[1
]}

Tielens, H. ^{[1
]}

Favia, P. ^{[1
]}

Rohr, E. ^{[1
]}

Hellings, G. ^{[2
,4
]}

Bender, H. ^{[1
]}

Roussel, P. ^{[1
]}

Crabbe, Y. ^{[1
]}

Brus, S. ^{[1
]}

Mannaert, G. ^{[1
]}

Kubicek, S. ^{[1
]}

Devriendt, K. ^{[1
]}

De Meyer, K. ^{[4
]}

Ragnarsson, L. -A. ^{[1
]}

Steegen, A. ^{[1
]}

Horiguchi, N. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium

[2] IWT, Brussels, Belgium

[3] FWO Vlaanderen, Brussels, Belgium

[4] Katholieke Univ Leuven, ESAT INSYS, Leuven, Belgium

[5] Sony, Zaventem, Belgium

[6] Panasonic, Asse, Belgium

[7] Fujitsu Semicond, Yokohama, Kanagawa, Japan

来源：

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2011年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si45Ge55/Si cap deposition and the workfunction metal, high performance devices with balanced V-t,V-sat (+0.12V, -0.16V) at scaled T-inv similar to 1nm and gate length L-g similar to 30nm are reported, leading to 17ps ring oscillators at 1 mu W/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.

引用

页数：4

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