A Subthreshold Source-Coupled Logic based Time-Domain Comparator for SAR ADC based Cardiac Front-Ends

被引：0

作者：

Routt, Samprajani ^{[1
]}

Babayan-Mashhaditt, Samaneh ^{[1
,2
]}

Serdijn, Wouter A. ^{[1
]}

机构：

[1] Delft Univ Technol, Sect Bioelect, Delft, Netherlands

[2] Eindhoven Univ Technol, Eindhoven, Netherlands

来源：

2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019) | 2019年

关键词：

time-domain comparator; source-coupled logic; low-voltage; biosignal acquisition;

D O I：

10.1109/apccas47518.2019.8953136

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low-voltage and low-power front-end design is required for the safe and long-term monitoring of cardiac signals. To address the low-voltage challenge, this paper presents a subthreshold source-coupled logic (STSCL) based time-domain comparator designed in 180 nm CMOS process technology. At a low supply voltage of 0.8 V, the STSCL time-domain comparator consumes 2.3 mu W at 1 MHz. Using 4 stages, the input referred noise and the offset of the comparator are 32 mu Vrms and 1.8 mV, respectively.

引用

页码：17 / 20

页数：4

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