Configurable CNN SoC Co-Processor Architecture

被引：1

作者：

Wijaya, Joshua Adiel ^{[1
]}

Adiono, Trio ^{[2
]}

机构：

[1] Inst Teknol Bandung, Sch Elect Engn & Informat, Bandung, Indonesia

[2] Univ Ctr Excellence Microelect, Inst Teknol Bandung, Bandung, Indonesia

来源：

2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2019年

关键词：

Convolution Neural Network (CNN); System on Chip (SoC); processor;

D O I：

10.1109/isocc47750.2019.9078513

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we proposed a configurable CNN architecture design for use in a SoC co-processor. The co-processor is configured and generated by the proposed design tools utilizing folding architecture and multiple processing elements working in parallel. The proposed system utilized a configurable system designer that can automatically generate the verilog source file that defines a CNN processor that can process various image and kernel sizes. The system designer also able to generate the program code to be run on the SoC platform. The system design has been verified using a ZYNQ (TM) 7000 SoC platform and shows the processing result is similar to the simulation results. The system can reach the processing speed of 72.727 MHz.

引用

下载

页码：281 / 282

页数：2

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