A host/co-processor FPGA-based architecture for fast image processing

A general system architecture for fast image processing, based on a Field Programmable Gate Array (FPGA) co-processor and a host computer, is presented and evaluated Images are transferred to the FPGA board via a high speed USB2.0 channel, implemented with a standard macrocell. A Lab VIEW host application controlling a frame grabber and an industrial camera is used to capture and exchange video data with the hardware co-processor. The FPGA accelerator is based on a Altera Cyclone H chip and is implemented as a system-ona-programmable-chip (SOPC) with the help of an embedded Nios II software processor. The SOPC system integrates the processor, external and on chip memory, the communication channel and a typical image filter appropriate for the evaluation of the system performance. Measured transfer rates over the communication channel and processing times for the implemented hardware filters are presented for various frame sizes. A range of applications is also discussed.