Architecture of an image rendering co-processor for MPEG-4 systems

The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-I multimedia standard. II is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-lime. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or software support for different video-formats. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 mu standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM I has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (CCIR).