An integrated co-processor architecture for a smartcard

A prototype VLSI design for a new smartcard co-processor for fast modular arithmetic with long integers is described. We present design criteria, objectives for selecting algorithms, the co-processor's structure, and some implementation details. Emphasis is also put on the manifold constraints which are faced when designing silicon for a smartcard, and on the optimization of algorithms in order to cope with these constraints without compromizing cryptographic strength. The co-processor is used in connection with a dedicated processor in order to make up a smartcard system capable of computing public key algorithms at top speed. (C) 1997 Academic Press Limited.