An integrated co-processor architecture for a smartcard

被引：0

作者：

Bock, H ^{[1
]}

Mayerwieser, W ^{[1
]}

Posch, KC ^{[1
]}

Posch, R ^{[1
]}

Schindler, V ^{[1
]}

机构：

[1] Graz Univ Technol, Inst Appl Informat Proc & Commun, A-8010 Graz, Austria

来源：

JOURNAL OF NETWORK AND COMPUTER APPLICATIONS | 1997年 / 20卷 / 04期

关键词：

D O I：

10.1006/jnca.1997.0048

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A prototype VLSI design for a new smartcard co-processor for fast modular arithmetic with long integers is described. We present design criteria, objectives for selecting algorithms, the co-processor's structure, and some implementation details. Emphasis is also put on the manifold constraints which are faced when designing silicon for a smartcard, and on the optimization of algorithms in order to cope with these constraints without compromizing cryptographic strength. The co-processor is used in connection with a dedicated processor in order to make up a smartcard system capable of computing public key algorithms at top speed. (C) 1997 Academic Press Limited.

引用

页码：323 / 337

页数：15

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