5V 8b 40MSample/s pipelined analog-to-digital converter

被引：0
|
作者：
Xue, L [1 ]
Shen, YZ [1 ]
Zhang, XM [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年
关键词：
A/D; pipelined; bootstrap; bottom-plate sampling;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a 5V 8b 40Msamples/s pipelined A/D converter is presented. The A/D converter contains seven stages and each stage realizes a resolution of 1.5bit. To reduce both linear and nonlinear errors, bottom-plate sampling, bootstrap and digital correction techniques are applied in ADC design. Accurate clocks are necessary for those techniques. Experiment results are obtained, with 1MHz input signal, the ADC acquired SNDR of 48.2dB SFDR of 58.2dB and 7.8 ENOB. The chip is fabricated in 0.35 m N-well CMOS technology and occupies an area of 4 mm2.
引用
收藏
页码：1559 / 1562
页数：4
相关论文
共 50 条
  • [41] An 8-b 1GS/s Fractional Folding CMOS Analog-to-Digital Converter with an Arithmetic Digital Encoding Technique
    Lee, Seongjoo
    Lee, Jangwoo
    Lee, Mun-Kyo
    Nah, Sun-Phil
    Song, Minkyu
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2013, 13 (05) : 473 - 481
  • [42] A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter
    Lu, Chi-Chang
    Lee, Tsung-Sum
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2007, 54 (08) : 658 - 662
  • [43] A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS
    Karrari, Hamid
    Andreani, Pietro
    Tan, Siyu
    2023 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE, NORCAS, 2023,
  • [44] An 8-bit 200 MS/s CMOS folding/interpolating analog-to-digital converter
    Heo, SC
    Jang, YC
    Park, SH
    Park, HJ
    IEICE TRANSACTIONS ON ELECTRONICS, 2003, E86C (04): : 676 - 681
  • [45] An 8-b 250-Msample/s Power Optimized Pipelined A/D Converter in 0.18-μm CMOS
    Hati, Manas Kumar
    Bhattacharyya, Tarun K.
    2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA), 2015,
  • [46] A 1.8V, 10-bit, 40MS/s MOSFET-Only pipeline analog-to-digital converter
    Charkhkar, Hamid
    Asadi, Alireza
    Lotfi, Reza
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 5363 - +
  • [47] An 8-bit, 8-GS/s Fquivalent Sampling Time Domain Analog-to-digital Converter
    Zhu, Yu
    Liu, Maliang
    Zhu, Zhangming
    2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2019,
  • [48] A low-power 4-b 2.5 gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder
    Radhakrishnan, S. (sradhakr@cs.wright.edu), Circuits and Systems Society, IEEE CASS; Science Council of Japan; The Inst. of Electronics, Inf. and Communication Engineers, IEICE; The Institute of Electrical and Electronics Engineers, Inc., IEEE (Institute of Electrical and Electronics Engineers Inc.):
  • [49] A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder
    Radhakrishnan, S
    Wang, MZ
    Chen, CIH
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 6142 - 6145
  • [50] A CMOS TRANSISTOR-ONLY 8-B 4.5-MS/S PIPELINED ANALOG-TO-DIGITAL CONVERTER USING FULLY-DIFFERENTIAL CURRENT-MODE CIRCUIT TECHNIQUES
    WU, CY
    CHEN, CC
    CHO, JJ
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (05) : 522 - 532
12345