5V 8b 40MSample/s pipelined analog-to-digital converter

被引：0
|
作者：
Xue, L [1 ]
Shen, YZ [1 ]
Zhang, XM [1 ]
机构：
[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China
来源：
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS | 2004年
关键词：
A/D; pipelined; bootstrap; bottom-plate sampling;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a 5V 8b 40Msamples/s pipelined A/D converter is presented. The A/D converter contains seven stages and each stage realizes a resolution of 1.5bit. To reduce both linear and nonlinear errors, bottom-plate sampling, bootstrap and digital correction techniques are applied in ADC design. Accurate clocks are necessary for those techniques. Experiment results are obtained, with 1MHz input signal, the ADC acquired SNDR of 48.2dB SFDR of 58.2dB and 7.8 ENOB. The chip is fabricated in 0.35 m N-well CMOS technology and occupies an area of 4 mm2.
引用
收藏
页码：1559 / 1562
页数：4
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