Embedded OTP fuse in CMOS logic process

被引：10
|
作者：
Lin, CY [1 ]
Lin, CH [1 ]
Ho, CH [1 ]
Liao, WW [1 ]
Lee, SY [1 ]
Ho, MC [1 ]
Wang, SC [1 ]
Huang, SC [1 ]
Lin, YT [1 ]
Hsu, CCH [1 ]
机构：
[1] Memory Technol Inc, Hsinchu 300, Taiwan
来源：
2005 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING - PROCEEDINGS | 2005年
关键词：
D O I：
10.1109/MTDT.2005.22
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the embedded OTP fuse in standard CMOS logic compatible process without additional mask. The embedded OTP fuse can be programmed in 100us per byte and be accessed in 6ns for 32 bits at once. The 32-bit OTP fuse takes less than 0.0085mm2 in 0.25um CMOS process and has 10-year data retention at 85 degrees C.
引用
收藏
页码：13 / 15
页数：3
相关论文
共 50 条
  • [1] Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies
    Chien, Sheng-Yen
    Lin, Po-Yen
    Chen, Hung-Yu
    Lin, Chrong-Jung
    King, Ya-Chin
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (11) : 3731 - 3736
  • [2] The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
    Hsieh, E. R.
    Huang, Z. H.
    Chung, Steve S.
    Ke, J. C.
    Yang, C. W.
    Tsai, C. T.
    Yew, T. R.
    2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2015,
  • [3] Logic compatible process technology for embedded atom switches in CMOS
    Okamoto, Koichiro
    Tada, Munehiro
    Banno, Naoki
    Iguchi, Noriyuki
    Sakamoto, Toshitsugu
    Hada, Hiromitsu
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2015, 54 (05)
  • [4] Ultra-fast, OTP-CMOS memory process speeds up embedded firmware development
    Fletcher, P
    ELECTRONIC DESIGN, 1997, 45 (15) : 48 - 48
  • [5] A rewritable CMOS-FUSE for system-on-chip with a differential cell architecture in a 0.13μm CMOS logic process
    Yamauchi, H
    Agata, Y
    Shirahama, M
    Kawasaki, T
    Nishihara, R
    Takahashi, K
    Kikukawa, H
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (10): : 1664 - 1672
  • [6] RESOLVING PLASMA INDUCED DAMAGE FOR A CMOS EMBEDDED-OTP TECHNOLOGY
    Duan, Xiaobo
    Chien, Wei-Ting Kary
    Zhang, Dennis
    Yu, Susie
    Zhao, Daniel
    Niu, Javen
    2016 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC), 2016,
  • [7] A Highly Scalable Interface Fuse for Advanced CMOS Logic Technologies
    Yang, Li-Yu
    Hsieh, Min-Che
    Liu, Jheng-Sin
    Chin, Yung-Wen
    Lin, Chrong Jung
    IEEE ELECTRON DEVICE LETTERS, 2012, 33 (02) : 245 - 247
  • [8] An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process
    Li, Y-L.
    Feng, P.
    Wu, N-J.
    EDSSC: 2008 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, 2008, : 100 - 103
  • [9] Embedded flash memory for security applications in a 0.13μm CMOS logic process
    Raszka, J
    Advani, M
    Tiwari, V
    Varisco, L
    Der Hacobian, N
    Mittal, A
    Han, M
    Shirdel, A
    Shubat, A
    2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 46 - 47
  • [10] The Demonstration of Gate Dielectric -fuse 4kb OTP Memory Feasible for Embedded Applications in High -k Metal-gate CMOS Generations and Beyond
    Hsieh, E. R.
    Chang, C. W.
    Chuang, C. C.
    Chen, H. W.
    Chung, Steve S.
    2019 SYMPOSIUM ON VLSI CIRCUITS, 2019, : C208 - C209
12345