Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs

被引：16
|
作者：
Pamarti, S [1 ]
Galton, I
机构：
[1] Rambus Inc, Los Altos, CA 94022 USA
[2] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92093 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2003年 / 50卷 / 11期
关键词：
delta-sigma modulator; fractional-N PLL; phased-locked loop (PLL); segmented digital-to-analog converter (DAC); synthesizer;
D O I：
10.1109/TCSII.2003.819117
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A theoretical analysis of a recently proposed phase-noise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in DeltaSigma fractional-N phased-locked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop bandwidth that can be achieved by PLLs incorporating the technique are quantified. Design guidelines are derived that enable customization of the technique, in terms of PLL target specifications.
引用
收藏
页码：829 / 838
页数：10
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