HLDTL: High-performance, low-cost, and double node upset tolerant latch design

被引：0
|
作者：
Yan, Aibin [1 ]
Huang, Zhengfeng [2 ]
Yi, Maoxiang [2 ]
Cui, Jie [1 ]
Liang, Huaguo [2 ]
机构：
[1] Anhui Univ, Sch Comp Sci & Technol, Hefei, Peoples R China
[2] Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei, Peoples R China
来源：
2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS) | 2017年
基金：
中国国家自然科学基金;
关键词：
single node upset; double node upset; soft error; latch design; RADIATION-HARDENED LATCH; SINGLE EVENT; CMOS;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a high-performance, low-cost, and double node upset (DNU) tolerant latch design. The latch mainly constructs from a 3-input Muller C-element at the output stage and a single node upset resilient cell for keeping data, and the cell mainly consists of triple mutual feedback 2-input Muller C-elements, thus the latch is DNU tolerant. Using fewer CMOS transistors, clock gating technique, and high-speed transmission path, the latch also performs with lower cost penalties. Simulation results have demonstrated the DNU tolerability and a similar to 97.78% area-power-delay product saving for the latch design on average compared with the DNU tolerant latch designs.
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收藏
页数：6
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