A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

被引：8
|
作者：
Farouk, Tamer [1 ]
Mohieldin, Ahmed Nader [1 ]
Khalil, Ahmed Hussien [1 ]
机构：
[1] Cairo Univ, Dept Elect Engn, Giza 12613, Egypt
来源：
MICROELECTRONICS JOURNAL | 2012年 / 43卷 / 01期
关键词：
Transconductor; Low-voltage; Low-power; Nonlinearity; Gm-C filters; Common-mode feedback (CMFB); Fully differential; CMOS;
D O I：
10.1016/j.mejo.2011.11.001
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V(pp) differential input is improved from -42 dB to -55 dB while operating from 1.0 V supply. As an example of the applications of the proposed transconductor, a 4th-order 5 MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130 nm CMOS process. It achieves THD of -53 dB for 0.4V(pp) differential input. It consumes 345 mu w from 1.0 V single supply. Theoretical and simulated results are in good agreement. (C) 2011 Elsevier Ltd. All rights reserved.
引用
收藏
页码：69 / 76
页数：8
相关论文
共 50 条
  • [21] Design of CMOS filter with low-voltage and low-power
    Li, ST
    Wu, J
    He, YG
    ICEMI '97 - CONFERENCE PROCEEDINGS: THIRD INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, 1997, : 447 - 450
  • [22] Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design
    Leung, KN
    Mok, PKT
    Ki, WH
    ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS, 1999, : 616 - 619
  • [23] Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design
    Leung, Ka Nang
    Mok, Philip K.T.
    Ki, Wing Hung
    Proceedings - IEEE International Symposium on Circuits and Systems, 1999, 2
  • [24] A LOW-VOLTAGE HIGHLY LINEAR MULTIPLE WEIGHTED INPUT CMOS TRANSCONDUCTOR
    CZARNUL, Z
    IIDA, T
    TSUJI, K
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1995, 42 (05): : 362 - 364
  • [25] Low-power rail-to-rail CMOS linear transconductor
    Popa, C
    2001 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOL 1 & 2, PROCEEDINGS, 2001, : 557 - 560
  • [26] Low-voltage highly-linear transconductor design in subthreshold CMOS
    Furth, PM
    Ommani, HA
    40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 156 - 159
  • [27] A low-voltage CMOS linear transconductor suitable for analog multiplier application
    Sawigun, Chutham
    Mahattanakul, Jirayuth
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 1543 - +
  • [28] Low-voltage and low-power CMOS voltage-to-current converter
    Liu, WH
    Liu, SI
    IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06): : 1029 - 1032
  • [29] Low-voltage low-power CMOS RF low noise amplifier
    Salama, Mohammed K.
    Soliman, Ahmed M.
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2009, 63 (06) : 478 - 482
  • [30] Low-power, low-voltage ADC is 0.05% linear
    Wettroth, J
    EDN, 1997, 42 (13) : 99 - 100
12345