Development of a deep-submicron CMOS process for fabrication of high performance 0.25 μm transistors

A process for fabrication of 0.25 mu m CMOS transistors has been demonstrated. NMOS transistors with drain current of 177 mu A/mu m at VC=VD=2.5 V and a PMOS transistors with drain current of 131 mu A/mu m at VG=VD=-2.5 V are reported. The threshold voltages are 1.0 V for the NMOS and -0.735 V for the PMOS transistors. The mask defined gate lengths are 0.5 mu m and 0.6 mu m for the NMOS and PMOS, respectively. Through a photoresist trimming process, the poly gate lengths are 0.25 mu m and 0.35 mu m or smaller. Electrical extraction of the gate lengths should yield effective gate lengths of 0.25 pm or smaller. These are the smallest transistors ever fabricated in the SMFL at RIT. Large off-state leakage is reported for the NMOS due to drain leakage induced by implant damage or aggressive titanium silicide formation. A better understanding of this leakage is being investigated and process recommendations given.