A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation

The scaling requirements of conventional DRAMs lead to the recent developments of capacitorless single-transistor (1T) DRAM in SOI technology. We propose a new concept of IT-DRAM (named MSDRAM), which is simple to fabricate, program, and read. Its basic mechanism is the metastable dip hysteresis effect, which takes advantage of the dynamic coupling between front and back interfaces in SOI transistors. Systematic measurements and simulations show that MSDRAMs are suitable for low-power applications, as they exhibit negligible OFF-state current and long retention time even for 50-nm devices.