A nanoscale vertical double-gate single-transistor capacitorless DRAM

被引：36

作者：

Ertosun, M. Guenhan ^{[1
]}

Cho, Hoon ^{[2
]}

Kapur, Pawan ^{[1
]}

Saraswat, Krishna C. ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Dept Elect Engn, Stanford, CA 94305 USA

[2] Intel Corp, Santa Clara, CA 95053 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2008年 / 29卷 / 06期

关键词：

double-gate (DG) MOSFETs; DRAM; floating-body DRAM; fully depleted; scaled CMOS; thin-body SOI;

D O I：

10.1109/LED.2008.922969

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We experimentally demonstrate and characterize a vertical (current flow that is perpendicular to the wafer) source (bottom)/drain (top) double-gate capacitorless single-transistor DRAM on a bulk silicon wafer. We have electrically measured retention times in excess of 25 ms. Device fabrication was facilitated by several key process innovations, which allow the device to also be integrated with planar devices using minimal additional process steps. The structure results in a highly scalable DRAM down to 22-nm technology node.

引用

页码：615 / 617

页数：3

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