A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation

被引：83

作者：

Bawedin, Maryline ^{[1
,2
]}

Cristoloveanu, Sorin ^{[3
]}

Flandre, Denis ^{[1
]}

机构：

[1] Catholic Univ Louvain, DICE, B-1348 Louvain, Belgium

[2] Univ Cambridge, Dept Engn, Cambridge CB3 OFA, England

[3] Inst Natl Polytech Grenoble, IMEP, F-38031 Grenoble, France

来源：

IEEE ELECTRON DEVICE LETTERS | 2008年 / 29卷 / 07期

关键词：

capacitorless; double gate; FinFET; floating-body; metastable dip (MSD) effect; SOI; 1T-DRAM;

D O I：

10.1109/LED.2008.2000601

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The scaling requirements of conventional DRAMs lead to the recent developments of capacitorless single-transistor (1T) DRAM in SOI technology. We propose a new concept of IT-DRAM (named MSDRAM), which is simple to fabricate, program, and read. Its basic mechanism is the metastable dip hysteresis effect, which takes advantage of the dynamic coupling between front and back interfaces in SOI transistors. Systematic measurements and simulations show that MSDRAMs are suitable for low-power applications, as they exhibit negligible OFF-state current and long retention time even for 50-nm devices.

引用

页码：795 / 798

页数：4

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