Submicron CMOS transient test structure for low power VLSI

A process patterning test structure with analog and digital circuits which contain various gate-width(W-G) and gate-length(L-G) combination is designed and fabricated for transient/AC performance verifications. Ultra-low power was observed from arrow gate-width and larger drain length test structure with same gate-length at various voltages, resulting in 10nA at 1v and 0.15mA at 5v for a W-G/L-G = 1 mu m/20 mu m CMOS ring oscillator because of high threshold voltage and low sleep-mode control though speed tradeoff due to low threshold voltage and high sleep-mode control is insignificant. Hence narrow, but properly optimized gate-width, and large drain length test structure at designated CMOS technology is promising for upcoming VLSI/USLI analog/digital low power designs.