Low Leakage Charge Recycling Power Gating Structure for CMOS VLSI Circuits

被引：0

作者：

Kavitha, M. ^{[1
]}

Govindaraj, T. ^{[2
]}

机构：

[1] Govt Coll Engn, Bargur, Tamil Nadu, India

[2] Muthayammal Engn Coll, Rasipuram, Tamil Nadu, India

来源：

INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS | 2015年 / 45卷 / 01期

关键词：

charge recycling; data retention; drowsy mode; leakage power; power gating; sleep mode; TECHNOLOGY;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Power dissipation has become an important factor in integrated circuits fabrication due to the rapid increase of battery powered hand held devices. In particular static dissipation increases considerably as technology scales down. To extend the battery lifetime of portable devices and ensure proper operation of digital circuits, static dissipation reduction needs to be addressed. In this paper, a low leakage charge recycling technique is proposed for this concern. The simulation results reveal that this technique exhibits 74 % leakage reduction, 37 % ground bounce reduction, 58 % Power Delay Product (PDP) reduction and nearly 10-33 % improvement in noise margin compared to conventional technique.

引用

页码：66 / 72

页数：7

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