A Digital Phase-locked Loop Based on MAP in PLC

被引：0
|
作者：
Lu Saijun [1 ]
Li Qianshu [2 ]
Mao Taiping [2 ]
机构：
[1] Guizhou Normal Univ, Inst Intelligent Informat Proc, Guiyang 550001, Peoples R China
[2] Ctr Sci Computat, Guiyang 550001, Peoples R China
来源：
ICEMI 2007: PROCEEDINGS OF 2007 8TH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOL IV | 2007年
关键词：
power line communication; impulsive noise; max a posteriori; digital phased-locked loop;
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
The conventional DPLLs (Digital Phase-locked Loops) are designed for Gaussian noise environment, and play important roles in carrier and clock recoveries. However, in power line communication (PLC), the power line noise is often impulsive, and then its statistical feature is different from Gaussian one. Therefore, we introduced Class A noise model in PLC first, and then proposed an optimum DPLL for such Class A noise environment using the techniques based on MAP (Maximum A Posteriori) estimating. The simulated results show the proposed DPLL has the smaller steady state phase errors than the conventional DPLL under Class A noise environment.
引用
收藏
页码：786 / +
页数：2
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