Test generation and fault simulation for cell fault model using stuck-at fault model based test tools

被引:14
|
作者
Psarakis, M [1 ]
Gizopoulos, D [1 ]
Paschalis, A [1 ]
机构
[1] NCSR Demokritos, Inst Informat & Telecommun, Athens 15310, Greece
关键词
cell fault model (CFM); stuck-at fault model; fault simulation; test pattern generation;
D O I
10.1023/A:1008389920806
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model. In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.
引用
收藏
页码:315 / 319
页数:5
相关论文
共 50 条
  • [1] Test generation and fault simulation for cell fault model using stuck-at fault model based test tools
    Inst of Informatics and, Telecommunications, Athens, Greece
    J Electron Test Theory Appl JETTA, 3 (315-319):
  • [2] Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools
    M. Psarakis
    D. Gizopoulos
    A. Paschalis
    Journal of Electronic Testing, 1998, 13 : 315 - 319
  • [3] Fault simulation and test generation for transistor shorts using stuck-at test tools
    Higami, Yoshinobu
    Saluja, Kewal K.
    Takahashi, Hiroshi
    Kobayashi, Shin-ya
    Takamatsu, Yuzo
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2008, E91D (03): : 690 - 699
  • [4] Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools
    Yu Zhang
    Bei Zhang
    Vishwani D. Agrawal
    Journal of Electronic Testing, 2014, 30 : 763 - 780
  • [5] Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools
    Zhang, Yu
    Zhang, Bei
    Agrawal, Vishwani D.
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2014, 30 (06): : 763 - 780
  • [6] Test generation for transistor shorts using stuck-at fault simulator and test generator
    Higami, Yoshinobu
    Saluja, Kewal K.
    Takahashi, Hiroshi
    Kobayashi, Shin-ya
    Takamatsu, Yuzo
    PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, : 271 - 274
  • [7] Stuck-at fault: A fault model for the next millennium
    Patel, JH
    INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 1166 - 1166
  • [8] Bridge fault diagnosis using stuck-at fault simulation
    Wu, J
    Rudnick, EM
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (04) : 489 - 495
  • [9] A method of test generation for path delay faults using stuck-at fault test generation algorithms
    Ohtake, S
    Ohtani, K
    Fujiwara, H
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 310 - 315
  • [10] Buying time for the stuck-at fault model
    Rearick, J
    INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 1167 - 1167