Two-dimensional signal Gating for low-power array multiplier design

被引：0

作者：

Huang, ZJ ^{[1
]}

Ercegovac, MD ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90024 USA

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Two-dimensional (2-D) signal gating schemes are proposed for low-power array multiplier design. 2-D gating provides gating lines for both multiplicand and multiplier operands. Different regions of the multiplier are dynamically deactivated according to the actual precision of each operand. Bit-level implementation is studied in order to minimize the gating overhead and make realistic evaluation. Compared to previous work, the 2-D signal gating is better in terms of power consumpiion, power-delay product and power-area product.

引用

页码：489 / 492

页数：4

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