On signal-gating schemes for low-power adders

被引：2
|
作者：
Huang, ZJ [1 ]
Ercegovac, MD [1 ]
机构：
[1] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90095 USA
来源：
CONFERENCE RECORD OF THE THIRTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1 AND 2 | 2001年
关键词：
D O I：
10.1109/ACSSC.2001.987047
中图分类号：
TP31 [计算机软件];
学科分类号：
081202 ; 0835 ;
摘要：
Signal gating schemes for low-power adder design are studied in this paper. Signal gating dynamically deactivates portions of an adder according to the actual precision of two operands. Based on program analysis, signal gating is developed for two different adders: symmetric adders and asymmetric adders. The effect of signal gating is investigated by incorporating several gating schemes into a RISC pipeline. Experimental results indicate more power saving compared to previous work.
引用
收藏
页码：867 / 871
页数：5
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