Two-dimensional signal gating for low power in high-performance multipliers

We propose two-dimensional signal gating for high-performance multipliers including tree multipliers and array multipliers with an upper/lower left-to-right leapfrog (ULLRLF) structure. In ULLRLF array multipliers, the G-Y gating line follows the boundary of existing upper/lower partitioning. The G-X gating line goes through the upper and lower LRLF arrays. In tree multipliers, the G-Y gating line follows the existing partitioning of tree branches. The G-X line goes through all carry-save adders for partial product reduction. Because of the irregularity of the tree reduction structure, signal gating in tree multipliers is more complex than that in array multipliers. Experimental results indicate that two-dimensional gating is quite efficient in high-performance multipliers, with 65% power reduction under test data with large dynamic range.