Area Optimization in 8T SRAM Cell for Low Power Consumption

被引：0

作者：

Sarker, M. S. Z. ^{[1
]}

Hossain, Mokammel ^{[1
]}

Hossain, Nozmul ^{[1
]}

Rasheduzzaman, Md ^{[1
]}

Islam, Md. Ashraful ^{[2
]}

机构：

[1] IIUC, Dept EEE, Chittagong, Bangladesh

[2] MIU, Dept CSE, Dhaka, Bangladesh

来源：

2015 INTERNATIONAL CONFERENCE ON ELECTRICAL & ELECTRONIC ENGINEERING (ICEEE) | 2015年

关键词：

CMOS logic; SRAM; VLSI; Power Consumption; LOW-VOLTAGE; REDUCTION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Cache memory plays an important role in high speed electronic devices. SRAM is the key element of cache memory. Cache memory is used for their high speed and SRAM is the element which provides speed to the cache. So this work is mainly concentrated on the simulation and analysis of 8T SRAM cells and their comparative analysis of different parameters such as width to length ratio, capacitance and power consumption. All the simulation has been carried out using Microwind and DSCH2 EDA tool.

引用

页码：117 / 120

页数：4

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