Hysteresis modeling in graphene field effect transistors

被引：9
|
作者：
Winters, M. [1 ]
Sveinbjornsson, E. O. [2 ]
Rorsman, N. [1 ]
机构：
[1] Chalmers Univ Technol, Dept Microtechnol & Nanosci, S-41296 Gothenburg, Sweden
[2] Univ Iceland, Inst Sci, IS-107 Reykjavik, Iceland
来源：
JOURNAL OF APPLIED PHYSICS | 2015年 / 117卷 / 07期
关键词：
ELECTRONIC TRANSPORT;
D O I：
10.1063/1.4913209
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage nu(g) versus the drain current i(d) reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi energy. The electron transport equations are then used to calculate the drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via a modified Preisach kernel. (C) 2015 AIP Publishing LLC.
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页数：9
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