Graphene field effect transistors with parylene gate dielectric

被引：94

作者：

Sabri, S. S. ^{[1
,2
]}

Levesque, P. L. ^{[1
]}

Aguirre, C. M. ^{[1
,3
,4
]}

Guillemette, J. ^{[1
,2
]}

Martel, R. ^{[1
,3
]}

Szkopek, T. ^{[1
,2
]}

机构：

[1] Regroupment Quebecois Mat Pointe, Montreal, PQ H3C 3J7, Canada

[2] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ H3A 2A7, Canada

[3] Univ Montreal, Dept Chim, Montreal, PQ H3C 3J7, Canada

[4] Ecole Polytech Montreal, Dept Genie Phys, Montreal, PQ H3C 3A7, Canada

来源：

APPLIED PHYSICS LETTERS | 2009年 / 95卷 / 24期

关键词：

field effect transistors; graphene; optical microscopy; organic compounds;

D O I：

10.1063/1.3273396

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene flakes. Room temperature mobilities of 10 000 cm(2)/Vs at 10(12)/cm(2) electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide.

引用

页数：3

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