Lateral punch-through TVS devices for on-chip protection in low-voltage applications

被引:7
|
作者
Urresti, J [1 ]
Hidalgo, S [1 ]
Flores, D [1 ]
Roig, J [1 ]
Cortés, I [1 ]
Rebollo, J [1 ]
机构
[1] CSIC, Ctr Nacl Microelect, IMB, Barcelona 08193, Spain
关键词
D O I
10.1016/j.microrel.2004.10.023
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel lateral punch-through TVs (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVs structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVs structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVs devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVs structures are compared with those of vertical punch-through TVs devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVs structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration. (c) 2004 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1181 / 1186
页数:6
相关论文
共 50 条
  • [1] Lateral Punch-Through TVS Devices: Design and Fabrication
    Urresti, Jesus
    Hidalgo, Salvador
    Flores, David
    Rebollo, Jose
    [J]. PROCEEDINGS OF THE 2009 SPANISH CONFERENCE ON ELECTRON DEVICES, 2009, : 148 - 151
  • [2] Punch-through diodes as replacement for low-voltage Zener diodes in ESD protection circuits
    van Dalen, R
    Koops, GEJ
    Pfennigstorf, O
    [J]. JOURNAL OF ELECTROSTATICS, 2004, 61 (3-4) : 149 - 169
  • [3] Novel Punch-through Diode Triggered SCR for Low Voltage ESD Protection Applications
    Bouangeune, Daoheung
    Vilathong, Sengchanh
    Cho, Deok-Ho
    Shim, Kyu-Hwan
    Leem, See-Jong
    Choi, Chel-Jong
    [J]. Journal of Semiconductor Technology and Science, 2014, 14 (06) : 797 - 801
  • [4] PUNCH-THROUGH GATE PROTECTION OF MOS DEVICES
    MILLER, CA
    POOLE, SJ
    [J]. MICROELECTRONICS AND RELIABILITY, 1982, 22 (02): : 187 - 193
  • [5] A quasi-analytical breakdown voltage model in four-layer punch-through TVS devices
    Urresti, J
    Hidalgo, S
    Flores, D
    Roig, J
    Rebollo, J
    Mazarredo, I
    [J]. SOLID-STATE ELECTRONICS, 2005, 49 (08) : 1309 - 1313
  • [6] Modellization of the breakdown voltage of four-layer punch-through TVS diodes
    Urresti, J
    Hidalgo, S
    Flores, D
    Roig, J
    Vellvehi, M
    Rebollo, J
    [J]. 2004 24TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, VOLS 1 AND 2, 2004, : 159 - 162
  • [7] High voltage tolerant on-chip ESD protection in low-voltage BiCMOS process
    Vashchenko, VA
    Kindt, W
    Hopper, P
    [J]. JOURNAL OF ELECTROSTATICS, 2006, 64 (02) : 104 - 111
  • [8] Optimisation of very low voltage TVS protection devices
    Urresti, J
    Hidalgo, S
    Flores, D
    Roig, J
    Rebollo, J
    Mazarredo, I
    [J]. MICROELECTRONICS JOURNAL, 2003, 34 (09) : 809 - 813
  • [9] A LOW-VOLTAGE TRIGGERING SCR FOR ON-CHIP ESD PROTECTION AT OUTPUT AND INPUT PADS
    CHATTERJEE, A
    POLGREEN, T
    [J]. IEEE ELECTRON DEVICE LETTERS, 1991, 12 (01) : 21 - 22
  • [10] Compact and Low Leakage Devices for Bidirectional Low-Voltage ESD Protection Applications
    Du, Feibo
    Qing, Yihong
    Hou, Fei
    Zou, Kepeng
    Song, Wenqiang
    Chen, Ruibo
    Liu, Jizhi
    Chen, Le
    Liou, Juin J.
    Liu, Zhiwei
    [J]. IEEE ELECTRON DEVICE LETTERS, 2021, 42 (03) : 391 - 394