Low-voltage and low-power adjustable differential delay line using the FGMOS transistor

被引：0

作者：

de la Cruz-Alejo, J. ^{[1
]}

Pastrana-Sedeno, J. A. ^{[1
]}

Gomez-Castaneda, F. ^{[1
]}

Moreno-Cadenas, J. A. ^{[1
]}

机构：

[1] CINVESTAV IPN, Dept Elect Engn, Mexico City, DF, Mexico

来源：

2008 7TH INTERNATIONAL CARIBBEAN CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a novel low-voltage and low-power analog differential delay line CMOS circuit design in the audio frequency range. The circuit is based on the G.-C linear integrator used as the main block in a low-pass filter which can be tuned varying a bias voltage. To overcome the dynamic range problems by the supply voltage reduction, the design is implemented using the FGMOS transistor. The simulated results in a 1.2 mu m CMOS technology show that delay time can be adjustable through 6 tap with a dissipation power of 140 mu W and a supply voltage of 1.5V.

引用

页码：87 / 92

页数：6

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