Sub-threshold 10T SRAM bit cell with read/write XY selection

被引：14

作者：

Feki, Anis ^{[1
,2
]}

Allard, Bruno ^{[2
]}

Turgis, David ^{[1
]}

Lafont, Jean-Christophe ^{[1
]}

Drissi, Faress Tissafi ^{[1
]}

Abouzeid, Fady ^{[1
]}

Haendler, Sebastien ^{[1
]}

机构：

[1] STMicroelectronics, Crolles, France

[2] Univ Lyon, INSA Lyon, CNRS, Ampere,UMR5005, F-69621 Villeurbanne, France

来源：

SOLID-STATE ELECTRONICS | 2015年 / 106卷

关键词：

Sub threshold Design; SRAM; Leakage; Half selected bit cells; Bit cell; XY selection; VOLTAGE; OPERATION;

D O I：

10.1016/j.sse.2014.11.018

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

New SRAM bit cell architectures have been proposed recently as solutions to the limitations of the sixtransistor (6T) SRAM bit cell in term of minimum supply voltage, V-DDMIN. There is no demonstrated bit cell as superior under ultra-low supply voltage like the 6T bit cell at nominal voltage. Main limitations concern first the ratio between the read current and the standby current at the lowest operating voltage, second the bit cell robustness to perturbations and third the data sensing sensitivity, among other but minor limitations. The paper presents two proposals of ten-transistor (10T) Ultra-Low-Voltage bit cell for 0.3 V operation and processed in 28 nm LP CMOS bulk. Simulation results are compared to experimental results to demonstrate a satisfying operation at Ultra-Low supply voltage. (C) 2014 Elsevier Ltd. All rights reserved.

引用

页码：1 / 11

页数：11

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