ULTRA WAFER THINNING AND DICING TECHNOLOGY FOR STACKED DIE PACKAGES

As the demand is increasing for memory cards, portable computing systems, multiple chip packages (MCPs), and other applications that require thin integrated circuits (ICs), the wafer thinning for advanced packaging methods become more and more important. This paper gives an overview of the different industrial wafer thinning and dicing techniques, including dicing after grinding (DAG), dicing before grinding (DBG), laser cut after grinding (LAG), and laser stealth dicing before grinding (SDBG). The process capability for each process was compared, and the challenges encountered during thinning and dicing the wafer to be 25 urn thickness are analyzed. Potential process issues have been investigated, including die strength and subsurface damage that is associated with these processes and mechanical properties, such as surface conditions and die warpage etc. Die strength test configurations and criteria are also included.