WAFER THINNING AND DICING TECHNOLOGY FOR 3D NAND FLASH

It is a main stream for 3-dimensional (3D) NAND flash which has the advantage of large storage capacity, excellent and reliable performance. Several different wafer architectures for 3D NAND flash including BICS (Bit Cost Scalable), TACT (Terabit Cell Array Transistor) and VG (Vertical Gate) etc. are all in mass production mode in current market. These new 3D NAND flash technologies are able to stack flash cells vertically in 32, 64, 96 layers or even more layers compared with 2D flash whose metallization layer is only single one. Therefore, the memory capacity in a 3D flash chip with these technologies can be increased dramatically to double, quadruple or more times than 2D flash one. However, more metallization layers on a wafer means more process stress to be introduced to the wafer itself. Thus, it will be a big challenge for wafer thinning and separation in IC assembly process later. This paper gives an overview of several different wafer thinning and separation technologies in IC packaging process. Potential process constraint or limitations, including die strength, side wall and sub-surface condition, are studied and associated with their wafer processes.