Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos

被引：0

作者：

Chen, TW ^{[1
]}

Huang, YW ^{[1
]}

Chen, TC ^{[1
]}

Chen, YH ^{[1
]}

Tsai, CY ^{[1
]}

Chen, LG ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, DSP IC Design Lab, Taipei 10764, Taiwan

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The most critical issue of an H.264/AVC decoder is the system architecture design with balanced pipelining schedules and proper degrees of parallelism. In this paper, a hybrid task pipelining scheme is first presented to greatly reduce the internal memory size and bandwidth. Block-level, macroblock-level, and macroblock/frame-level pipelining schedules are arranged for CAVLD/IQ/IT/INTRA_PRED, INTER_PRED, and DEBLOCK, respectively. Appropriate degrees of parallelism for each pipeline task are also proposed. Moreover, efficient modules are contributed. The CAVLD unit smoothly decodes bitstream into symbols without bubble cycles. The INTER_PRED unit highly exploits the data reuse between interpolation windows of neighboring blocks to save 60% of external memory bandwidth. DEBLOCK unit doubles the processing capability of our previous work with only 35.3% of logic gate count overhead. The proposed baseline profile decoder architecture can support up to 2048x1024 30fps videos with 217K logic gates, 10KB SRAMs, and 528.9MB/s bus bandwidth when operating at 120MHz.

引用

页码：2931 / 2934

页数：4

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