A Design of High-Performance Pipelined Architecture for H.264/AVC CAVLC Decoder and Low-Power Implementation

In this paper, we propose a highly efficient VLSI architecture for context-based adaptive variable-length coding (CAVLC) decoder. In multimedia data processing systems, the real-time processing requirement is the most critical problem and the only requirement that must be satisfied. Thus, an architecture which has a short processing time though a high throughput, can meet the requirement at low operating frequencies. Consequently, the architecture can have an advantage of low power consumption. We propose two methods to improve the throughput of CAVLC decoders. The first method eliminates the pipeline hazard in a pipelined architecture for CAVLC decoder. The second method expands the capacity of the barrel shifter. Experimental results show that the proposed architecture can improve throughput by about 45%. As a result, the proposed architecture greatly reduces the operating frequency for real-time processing, which is the key factor of reducing power consumption. The synthesis result shows that the design achieves the maximum operating frequency at 125 MHz, and the hardware cost is about 12.6K under a 0.18 um CMOS process(1).