High performance architecture design of CAVLC encoder in H.264/AVC

被引：8
|
作者：
Hu Hongqi [1 ]
Sun Jingnan [2 ]
Xu Jiadong [1 ]
机构：
[1] Northwest Polytech Univ, Sch Elect & Informat, Xian 710072, Peoples R China
[2] Zhejiang Gongshang Univ, Coll Stat & Comp Sci, Hangzhou 310012, Peoples R China
来源：
CISP 2008: FIRST INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOL 1, PROCEEDINGS | 2008年
关键词：
D O I：
10.1109/CISP.2008.541
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Context-based adaptive variable length coding (CAVLC) is a new and important feature of the H.264/AVC. Based on analysis and modification of the conventional run-length coding architecture, a novel high efficiency VLSI architecture for H.264/AVC CAVLC encoding is presented in this paper. An approach called arithmetic table structure is exploited to replace look-up-table ROM for reducing hardware resource. Moreover, a modified VLC packer is used to increase the throughout of CA VLC encoder architecture. With the synthesis constrain of 133MHz, the hardware cost of the proposed design is 13113 gates based on 0.18 CMOS technology. Simulations show that the proposed design is capable of real-time processing for 1920x1080 30fps videos.
引用
收藏
页码：613 / +
页数：2
相关论文
共 50 条
  • [1] Design of high-speed CAVLC decoder architecture for H.264/AVC
    Oh, Myungseok
    Lee, Wonjae
    Jung, Yunho
    Kim, Jaeseok
    [J]. ETRI JOURNAL, 2008, 30 (01) : 167 - 169
  • [2] A high performance CAVLC encoder design for MPEG-4 AVC/H.264 video coding applications
    Chien, Chih-Da
    Lu, Keng-Po
    Shih, Yi-Hung
    Guo, Jiun-In
    [J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 3838 - +
  • [3] An area reduction scheme for the H.264/AVC CAVLC encoder
    Rahman, Choudhury A.
    Badawy, Wael
    [J]. 2008 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-12, 2008, : 1021 - 1024
  • [4] Design of high speed cavlc decoder for H.264/AVC
    Oh, Myungseok
    Lee, Wonjae
    Kim, Jaeseok
    [J]. 2007 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, VOLS 1 AND 2, 2007, : 325 - 330
  • [5] Design of High Performance Arithmetic Encoder for CABAC in H.264/AVC
    Kim, Yoonsup
    Moon, Jeonhak
    Choi, Wonjoon
    Lee, Seongsoo
    Lee, Seok
    Woo, Dockha
    [J]. MINO'09: PROCEEDINGS OF THE 8TH WSEAS INTERNATIONAL CONFERENCE ON MICROELECTRONICS, NANOELECTRONICS, OPTOELECTRONICS: ADVANCES IN MICROELECTRONICS, NANOELECTRONICS AND OPTOELECTRONICS, 2009, : 103 - +
  • [6] Architecture Design for the Context Formatter in the H.264/AVC Encoder
    Pastuszak, Grzegorz
    [J]. PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2006, : 71 - 72
  • [7] System architecture design methodology for H.264/AVC encoder
    Chang, Samuel C.
    Cheng, Chih-Chi
    Chen, Liang-Gee
    [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2, 2007, : 304 - +
  • [8] An improved CAVLC entropy encoder of H.264/AVC and FPGA implementation
    Guo, Hui
    Fu, Yong-qing
    [J]. ADVANCED MATERIALS AND COMPUTER SCIENCE, PTS 1-3, 2011, 474-476 : 241 - 246
  • [9] High performance VLSI architecture design for H.264 CAVLC decoder
    Alle, Mythri
    Biswas, J.
    Nandy, S. K.
    [J]. IEEE 17TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS, 2006, : 317 - +
  • [10] A HIGH-PERFORMANCE CABAC ENCODER ARCHITECTURE FOR HEVC AND H.264/AVC
    Zhou, Jinjia
    Zhou, Dajiang
    Fei, Wei
    Goto, Satoshi
    [J]. 2013 20TH IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP 2013), 2013, : 1568 - 1572
12345