Architecture Design for the Context Formatter in the H.264/AVC Encoder

被引：0
|
作者：
Pastuszak, Grzegorz [1 ]
机构：
[1] Warsaw Univ Technol, Inst Radioelect, Warsaw, Poland
来源：
PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. This paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. The implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders.
引用
收藏
页码：71 / 72
页数：2
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