System architecture design methodology for H.264/AVC encoder

MPEG-4 H.264/AVC [1] has become a joint standard for ITU-T and MPEG and has been implemented in a wide spectrum of applications, from digital video broadcasting for handsets (DVB-H) to Hi-Definition DVD Storage (HD DVD). However, the resolution and system clock rate requirements vary greatly. Therefore, developing a system that is optimal for all applications is impossible. Among all aspects of the H.264 encoding system architecture design, inter-prediction occupies 99% total computation complexity and the search-range buffer occupies 76% of total on-chip memory [11 [2]. Our design methodology fully explores the design spaces of parallelism of inter-prediction, macro-block (MB) pipelining, and search-range buffer architecture. This paper combined with [3] presents a complete methodology to help H.264/AVC systems designers obtain the most area efficient design under user defined timing requirements.