High performance architecture design of CAVLC encoder in H.264/AVC

被引：8
|
作者：
Hu Hongqi [1 ]
Sun Jingnan [2 ]
Xu Jiadong [1 ]
机构：
[1] Northwest Polytech Univ, Sch Elect & Informat, Xian 710072, Peoples R China
[2] Zhejiang Gongshang Univ, Coll Stat & Comp Sci, Hangzhou 310012, Peoples R China
来源：
CISP 2008: FIRST INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING, VOL 1, PROCEEDINGS | 2008年
关键词：
D O I：
10.1109/CISP.2008.541
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Context-based adaptive variable length coding (CAVLC) is a new and important feature of the H.264/AVC. Based on analysis and modification of the conventional run-length coding architecture, a novel high efficiency VLSI architecture for H.264/AVC CAVLC encoding is presented in this paper. An approach called arithmetic table structure is exploited to replace look-up-table ROM for reducing hardware resource. Moreover, a modified VLC packer is used to increase the throughout of CA VLC encoder architecture. With the synthesis constrain of 133MHz, the hardware cost of the proposed design is 13113 gates based on 0.18 CMOS technology. Simulations show that the proposed design is capable of real-time processing for 1920x1080 30fps videos.
引用
收藏
页码：613 / +
页数：2
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