A HIGH-PERFORMANCE CABAC ENCODER ARCHITECTURE FOR HEVC AND H.264/AVC

被引：0
|
作者：
Zhou, Jinjia [1 ]
Zhou, Dajiang [1 ]
Fei, Wei [1 ]
Goto, Satoshi [1 ]
机构：
[1] Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka 8080135, Japan
来源：
2013 20TH IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING (ICIP 2013) | 2013年
关键词：
CABAC; entropy coding; HEVC; UHDTV;
D O I：
暂无
中图分类号：
TB8 [摄影技术];
学科分类号：
0804 ;
摘要：
This paper presents a high-performance context adaptive binary arithmetic coding (CABAC) architecture for the next-generation UHDTV applications. Its maximum throughput has been enhanced by 31%-34% with the proposed pre-normalization (prenorm.), hybrid path coverage (HPC), bypass bin splitting (BPBS) and state dual-transition (SDT) schemes. Both the HEVC and H.264/AVC formats can be supported with our architecture by applying a dual-standard binarization design. The proposed CABAC architecture has been silicon proven in a 65nm video encoder chip. It delivers 4.27 similar to 4.40bins/cycle with synthesized and measured clock rates of 401.5MHz and 330MHz, respectively. Therefore a high performance of 1.452Gbin/s is achieved for real-time UHDTV encoding.
引用
收藏
页码：1568 / 1572
页数：5
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