Hardware architecture design of CABAC codec for H.264/AVC

被引：0
|
作者：
Li, Lingfeng [1 ]
Song, Yang [1 ]
Ikenaga, Takeshi [1 ]
Goto, Satoshi [1 ]
机构：
[1] Waseda Univ, Grad Sch Informat Prod & Syst, Tokyo, Japan
来源：
2007 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS | 2007年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0. IS [uri technology. Results show that the equivalent gate counts is 33.2k when the maximum frequency is 230MHz. It is estimated that the proposed CABAC codec can process the input binary symbol at 135Mb/s for encoding and 90Mb/s for decoding.
引用
收藏
页码：248 / +
页数：2
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