A high-performance VLSI architecture for CABAC decoding in H.264/AVC

被引：1
|
作者：
Li Bingbo [1 ]
Zhang Ding [1 ]
Fang Jian [1 ]
Wang Lianghao [1 ]
Zhang Ming [1 ]
机构：
[1] Zhejiang Univ, Dept Informat Sci & Elect Engn, Hangzhou 310027, Peoples R China
来源：
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年
关键词：
D O I：
10.1109/ICASIC.2007.4415749
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A mixed hardware/software architecture for CABAC decoding in H.264/AVC is proposed in this paper. For the purpose of flexibility, ctxIdx calculation process is implemented by software, while others are implemented by hardware. An optimized parallel decoding architecture that allows decoding two binary symbols at one clock cycle is designed to enhance overall decoding performance. An efficient scheme of accessing context models is presented. Experimental results show that the proposed architecture improves the decoding performance by 20% compared to conventional scheme. The proposed design can achieve HDTV 1080i video processing requirement when operated at 140MHz.
引用
收藏
页码：790 / 793
页数：4
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